Technical Field
The present disclosure relates to bipolar transistors formed on an integrated circuit. More specifically, the present disclosure relates to a method for manufacturing such a transistor.
Description of the Related Art
In integrated circuits, it may be advantageous to integrate, on a same wafer, MOS transistors and bipolar transistors (integration better known as “BiCMOS”). Indeed, these two types of transistors have specific advantages. In particular, MOS transistors allow fast switchings for digital processings, while bipolar transistors have a particularly good performance at high frequencies, for example, higher than some hundred GHz, and may have a high output power. Thus, these last transistors may be used to form circuits for controlling optical circuits, for example, lasers.
Thus, methods for simultaneously manufacturing MOS transistors and bipolar transistors on a same substrate are needed.
FIG. 1 illustrates an example of a conventional bipolar transistor formed on a solid substrate where MOS transistors can also be formed.
At the surface of a solid substrate 10 is defined an active area delimited by deep insulating trenches 12. Trenches 12 are conventionally formed and are currently known as DTI (for Deep Trench Isolation) trenches.
A heavily-doped region 14 forming the collector of the bipolar transistor extends in depth in the active area of substrate 10 delimited by trenches 12. Region 14 extends in depth in substrate 10 across a thickness on the order of 1 μm, leaving a less heavily-doped layer 16 at the substrate surface.
Shallow trenches 18, currently known as STI (for Shallow Trench Isolation) trenches, are provided on either side of the active area and stop deep in region 14. In the middle of shallow trenches 18 are provided regions 20 of access to collector region 14. Regions 20 are in practice a heavily-doped region of substrate 10.
At the surface of substrate 10 is formed a stack of an insulating layer 22, for example, an oxide, and of a heavily-doped polysilicon layer 24 (of type P if the transistor is an NPN transistor). The stack of layers 22 and 24 extends above the apparent surface of substrate 10 (region 16) and stops above a portion of shallow trench 18. Opposite to region 16, a portion of insulating layer 22 is replaced with a stack 25 of a silicon-germanium layer and of a silicon layer. Stack 25 forms the base of the bipolar transistor.
An opening is also provided in layer 24, opposite to region 16 and on a smaller surface area than the opening in region 22. In this opening defined in layer 24, as well as at the surface of layer 25, a heavily-doped region 26 forming the emitter region of the bipolar transistor is provided. Region 26 is separated from layer 22 by spacers 28 made of insulating material.
An emitter contact 29 is provided on semiconductor material 26 via a silicide layer 30 formed at the surface of semiconductor material 26. A base contact 32 is provided on layer 24 via a silicide layer 34 formed at the surface of layer 24, and a collector contact 36 is provided on regions 20 via a silicide layer 38 formed at the surface of these regions.
To obtain the device of FIG. 1, the following steps may be carried out. At an initial step, heavily doped region 14 is formed in depth in a semiconductor substrate 10. A semiconductor material epitaxy may then be performed to obtain a less heavily doped region 16 of adapted thickness. Insulating trenches 12 for delimiting the active area, as well as trenches 18, are then defined (by means of adapted masks). The dopant implantation enabling to form regions 20 is then performed.
Then, an insulating material layer (having region 22 forming a portion thereof at the end of the manufacturing) is formed over the entire active region, after which a heavily-doped polysilicon layer (having region 24 forming a portion thereof at the end of the manufacturing) is formed at the surface of the substrate. A dopant implantation is then performed in region 16, through the insulating material present above this region, to form a collector region localized in this region. An opening is then formed in heavily-doped polysilicon layer 24 opposite to region 16, this opening corresponding to the final opening defined in layer 24. An insulating material layer is then formed at the surface of layer 24 and on the walls of the previously-defined opening.
An etching is then performed from the bottom of the opening defined in layer 24 to remove the material of insulating layer 22 under the opening, but also to laterally define a cavity in the layer of material 22, under layer 24.
A silicon-germanium growth is then carried out in the cavity thus defined. Silicon-germanium 25 grows from the lower surface of polysilicon layer 24 as well as from the upper surface of region 16, to fill the cavity formed in insulating layer 22. Then, spacers 28 are formed at the surface of silicon-germanium region 25. The opening remaining at the surface of silicon-germanium layer 25 is then filled with material 26 forming the transistor emitter.
A last step comprises performing etchings to obtain the topology of the transistor of FIG. 1 and thus to expose the upper surfaces of regions 20 and 24, after which a silicidation of the device is carried out to form silicide regions 30, 34, and 38.
A first disadvantage of a bipolar transistor such as that in FIG. 1 is its bulk. Indeed, in order to operate properly, collector region 14 typically has, in substrate 10, a depth on the order of one micrometer. Such a depth is not compatible with recent methods for manufacturing MOS transistors on substrates of silicon-on-insulator type (SOI) where the upper substrate is very thin (thickness smaller than 15 nm). Such substrates, currently used in new semiconductor technologies, are called FD-SOI (fully depleted semiconductor on insulator).
Further, with the device of FIG. 1, the access to the base is performed via a layer 24 of heavily-doped polysilicon, the contact between layer 24 and silicon-germanium region 25 being achieved on a horizontal surface. This contact is illustrated in FIG. 1 by a region in dotted lines 39.
The use of a polysilicon layer to access the base alters the transistor performance. Indeed, polysilicon has a higher resistivity than, for example, a metal or heavily-doped single-crystal silicon. Thus, there is a significant access resistance between base contact 32 and base 25, which is not desired. It should be noted that the forming of single-crystal silicon for the access to the base is not compatible with the above method, a growth or a deposition of single-crystal silicon being impossible to perform on an insulating material.
Further, with the device of FIG. 1, the junction between base region 25 and collector region 16 has a relatively extensive surface area, which implies a significant junction capacitance between these two regions. To obtain a bipolar transistor having a satisfactory performance, it is desired for the junction capacitances to be as low as possible.
Thus, the bipolar transistor of FIG. 1 has junction capacitances and access resistances which are generally not compatible with a high-performance bipolar transistor.
Thus, there is a need for a method for manufacturing a high-performance bipolar transistor on a substrate of FD-SOI type.